This invention relates generally to nonvolatile programmable memory circuits and is particularly directed to the prevention of inadvertent write operations in a nonvolatile programmable read only memory by a microprocessor arising from supply voltage variations.
When power is applied to a system incorporating a microprocessor, the microprocessor is typically energized after a suitable safe time delay allowing for system stabilization for providing various, well-defined power supply levels thereto. After the microprocessor is initially energized, it is reset to an initial set of conditions and begins executing instructions at a start address within its read only memory (ROM). The operating program stored within the microprocessor's ROM then controls its operation in sequentially executing the various instructions stored therein.
In a microprocessor controlled system, there is frequently a nonvolatile programmable memory device in which is stored operating instructions and data for executing a specific task stored within the microprocessor's ROM. Where the memory device is a programmable read only memory (PROM) the information stored within the memory device may be updated by the microprocessor in accordance with varying system conditions and requirements. Thus, data may be either written into or read from selected memory locations within the PROM by the microprocessor.
The microprocessor and the PROM are designed to operate at a specified voltage level which typically is on the order of 5 VDC. However, these devices will operate at lower voltages, although in a frequently degraded, unreliable state. For example, a nonvolatile PROM which is designed to operate at 4.75 VDC may operate in a degraded mode with a supply voltage as low as 3.0 VDC. The microprocessor similarly possesses a supply voltage range over which it will operate, but in a diminished capacity. A microprocessor is typically provided with a RESET input to ensure that it is properly initialized only after its supply voltage has reached, or is at, a predetermined level. Similarly, a nonvolatile programmable memory device typically includes internal circuitry which precludes its operation below a predetermined threshold voltage level. This threshold voltage is typically set at a voltage substantially less, e.g., 3.0 VDC, than the nominal operating voltage of the memory device due to the wide tolerances inherent in the fabrication of these integrated circuits. This prevents the memory device from transitioning to an inactive state in response to small variations in the power supply voltage. Therefore, the nonvolatile programmable memory device is generally capable of operating within the supply voltage range of 3.0 to 4.5 VDC wherein it is subject to erroneous write commands from the microprocessor. These erroneous write commands cause the loss of previously stored data as well as the storage of erroneous data in the nonvolatile programmable memory device due to the nonvolatility of the write operation therein.
The present invention is intended to avoid the aforementioned problem encountered in the prior art by providing write protection for a nonvolatile PROM in the event of inadvertent microprocessor generated write commands arising from supply voltage transisents including system power up and power down.